Intrinsic RESET Speed Limit of Valence Change Memories

During the last decade, valence change memory (VCM) has been extensively studied due to its promising features, such as a high endurance and fast switching times. The information is stored in resistive state (logcial '0', HRS) low '1', LRS). It can also be operated two different writing schemes, namely unipolar mode (LRS HRS are written at same voltage polarity) bipolar opposite polarities). VCM, however, still suffers from large variability during operations faults occur, which not yet fully understood and, therefore, require better understanding of underlying fault mechanisms. In this study, new intrinsic failure mechanism identified, prohibits RESET times (transition LRS faster than 400 ps possibly limits endurance. We demonstrate speed limitation by measuring kinetics devices (namely Pt/TaO$_\mathrm{x}$/Ta Pt/ZrO$_\mathrm{x}$/Ta) time regime 50 ns ps, corresponding fastest reported for VCM. Faster were achieved increasing applied pulse voltage. Above threshold it was, no longer possible reset both types devices. Instead SET LRS) event occurred, preventing occurrence attributed an oxygen exchange interface Pt~electrode, suppressed introducing blocking layer interface, allowed